Please use this identifier to cite or link to this item: http://dspace.ensta.edu.dz/jspui/handle/123456789/440
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dc.contributor.authorLOUNNACI, Sarah-
dc.contributor.authorBENDOUDA, Djamila (Directeur de thèse)-
dc.contributor.authorHLADIK, Pierre-Emmanuel (Directeur de thèse)-
dc.contributor.authorMAIZA, Claire (Directeur de thèse)-
dc.date.accessioned2026-10-07T08:42:50Z-
dc.date.available2026-10-07T08:42:50Z-
dc.date.issued2025-
dc.identifier.urihttp://dspace.ensta.edu.dz/jspui/handle/123456789/440-
dc.descriptionProjet de fin d’étude d'ingeniorat: Systèmes Embarqués:Alger: Ecole Nationale Supérieure des Technologie Avancées: 2025en_US
dc.description.abstractConvolutional Neural Networks (CNNs) have become indispensable in Artificial In- telligence applications due to their ability to automatically extract hierarchical features. However, when deployed in real-time and embedded systems, accuracy is not the only metric of interest. In such environments, timing predictability and the guarantee of meet- ing strict deadlines are essential. This work addresses this challenge by bridging Deep Learning inference with real-time analysis through the systematic transformation of CNN models into Directed Acyclic Graphs (DAGs). The primary contribution of this project is the design of MIND Model Inference Net- work Designer software, which automatically extracts the inference structure of a CNN and converts it into a DAG compatible with the MIA Multicore Interference Analysis tool. To capture different execution strategies, we developed a set of novel and innova- tive regrouping policies, such as Macroscopic Layer-Wise Modeling (MLWM), Structured Spatial Partitioning (SSP), Redundant Convolution via Channel Tiling (RCCT), and Dense Fusion (DF). These policies balance computation, memory access, and communi- cation overheads in parallel, making it possible to analyze their impact on the many-core Kalray MPPA architectures. Furthermore, we proposed architecture-aware cost for Kalray’s architectures: Bostan 256 cores and Coolidge 80 cores with TCA co-processor. By formalizing the Worst-Case Execution Time (WCET) and Worst-Case Memory Access (WCMA) at different preci- sions FP32, FP16, INT8, we provided a relatively accurate computation model that en- ables Worst-Case Response Time (WCRT) computation through MIA. The testing phase validates our methodology with a prototype CNN and multiple parameter variations, highlighting the trade-offs between speedup, compute efficiency, interference, memory transfer costs, etc. This work demonstrates the feasibility of systematically analyzing CNNs for Real- Time Systems on many-core processors, achieving a complete workflow: from CNN to DAG extraction, to regrouping policy application, cost modeling, YAML generation, and MIA-based timing analysis. The outcomes not only validate the proposed approach but also open perspectives for extending analysis to larger models.en_US
dc.language.isoenen_US
dc.subjectDeep Learningen_US
dc.subjectConvolutional Neural Networksen_US
dc.subjectDirected Acyclic Graphen_US
dc.subjectReal-Time Systemsen_US
dc.subjectKalray MPPAen_US
dc.subjectWCETen_US
dc.subjectWCMAen_US
dc.subjectWCRTen_US
dc.titleAutomatic Extraction of the Inference Structure of a CNN as a DAG for Temporal Analysis of Many-Core Systemsen_US
dc.typeThesisen_US
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